A phase locked loop (PLL) is a closed loop frequency control system. The PLL adjusts the frequency of an internal signal until the phase of an internal signal is substantially the same as the phase of a reference signal (e.g., an external clock signal) to which the internal signal is “locked.” When either the PLL is initially powered or the internal signal or reference signal is first applied to the PLL, the phase of the internal signal generally will be quite different from the phase of the reference signal. The PLL then adjusts the phase of the internal signal until it is aligned with the phase of the reference signal, and the PLL is thus locked with the reference signal.
There are many types of prior art PLLs available, one of which is a charge pump PLL 100 as shown in FIG. 1. The charge pump PLL 100 of FIG. 1 includes a phase detector 110, a charge pump 102, a filter 104, a voltage controlled oscillator 106, and an N frequency divider circuit 108 connected to each other as shown. The phase detector 110 compares the phases of two input signals, an external clock signal 112 and a feedback clock signal 114. The phase detector 100 then generates an UP_signal 120 or a DN_signal 122 depending on the phase difference between the two input signals 112 and 114. The UP_signal 120 and the DN_signal 122 are applied to a charge pump 102, which generates a voltage having a magnitude that changes in one direction in response to the UP_signal 120 and in the other direction in response to the DN_signal 122. The voltage from the charge pump 102 passes through the filter 104 to control the dynamic performance of the PLL 100. The filter 104 then outputs a control signal (“Vct”) 124, or a phase error signal, that is applied to the voltage controlled oscillator 106 (“VCO”). The VCO 106 generates a periodic output clock signal having a frequency corresponding to (e.g., that is controlled by) the control signal Vct 124.
The output signal of the phase detector 110 causes the charge pump 102 and filter 104 to adjust the magnitude of the control signal Vct 124 to either increase or decrease the frequency of the output clock signal 116 generated by the voltage control oscillator 106. More specifically, the control signal Vct 124 has a magnitude that increases responsive to the UP_signal 120 and decreases responsive to the DN_signal 122. The control signal Vct 124 adjusts the frequency of the feedback clock signal 114 until the phase (which is the integral to the frequency) of the feedback clock signal 114 is equal to the phase of the external clock signal 112 so that the PLL 100 is locked. When the PLL is locked, the frequency of the feedback clock signal 114 will, of course, be equal to the frequency of the external clock signal 112. The feedback clock signal 114 may go through an N divider circuit 108 before being fed back into the phase detector 110 so that the frequency of the output clock signal 116 will be N times greater than the frequency of the external clock signal 112. The output clock signal 116 is then output from the PLL 100.
FIG. 2 is an example signal timing diagram illustrating the various signals that may be generated during a typical operation of the prior art PLL 100 in FIG. 1. At time t1 the external clock signal 112 leads the feedback clock signal 114 by the difference of t0 and t1. In response to a rising edge of the external clock signal 112 at time t0, the phase detector 110 drives the UP_signal 120 low. At time t1 and in response to a rising edge of the feedback clock signal 114, the phase detector 110 drives the UP_signal 120 high. Therefore, the phase detector 110 generates the UP_signal 120 as a negative pulse having a width proportional to the time the feedback clock signal 114 lags the external clock signal 112 to increase the frequency of the feedback clock signal 114. Conversely, at time t5 the external clock signal 112 lags the feedback clock signal 114 by the difference of t4 and t5. In response to a rising edge of the feedback clock signal 114 at time t4, the phase detector 110 drives the DN_signal 122 high. At time t5 and in response to a rising edge of the external clock signal 112, the phase detector 110 drives the DN_signal 122 low. Thus, the phase detector 110 generates the DN_signal 122 as a positive pulse on the DN_signal 122 having a width proportional to the time the feedback clock signal 114 leads the external clock signal 112 to decrease the frequency of the feedback clock signal 114.
The PLL 100 will continue to generate appropriate negative UP_signals 120 or positive DN_signals 122 until the feedback clock signal 114 is in phase and thus at the same frequency as the external clock signal 112 to keep the PLL 100 in lock. With further reference to FIG. 2, at time tn a rising edge of the external clock signal 112 is at nearly the same time as the rising edge of the feedback clock signal 114. Therefore, the PLL 100 locks.
The time it takes the PLL 100 to lock is typically an important parameter of the PLL. This is due, in part, to the fact that the PLL is not really usable for its intended purpose until the PLL 100 is locked. Traditionally, one technique that has been used to reduce the lock time has been to increase the loop gain. Once the loop gain exceeds a certain range, however, increasing the loop gain may increase the lock time, rather than reducing the lock time. In addition to increasing the lock time, very high loop gains often result in loop instability. If a PLL is unstable, the PLL will not lock and will not function properly. An example of instability in PLL occurs when the charge pump continuously overcompensates for the phase difference of the two input signals.
Therefore, there is a need for a PLL having a relatively short lock time while maintaining stability of the PLL.